Solid-state storage devices employing non-volatile semiconductor memory such as NAND flash memory typically use block or page read counters as an indicator that checks should be made for memory blocks or pages that may be subject to read disturb errors. When a page or block counter, counting up or down, reaches a limit value, the solid-state drive (SSD) controller instigates a check of pages or memory blocks that may be affected by read disturb errors following the number of reads of the page or memory block monitored by the counter. Read disturb errors cause the data in neighboring pages within the memory block to change due to a weak programming effect of wordlines adjacent to the page or memory block being read.
Typically, block and page counters are employed with programmable limits but with no attempt to limit the number of counters that may hit the limits at any given time. With uncontrolled and unpredictable workloads, the only limit to the number of memory block and page counters that may simultaneously reach their limit for checking within a period is the rate of read commands to the memory, which in fast SSDs could exceed 1 million/second. A ‘storm’ occurs in a read disturb counter limit scheme where large numbers of counters may be allowed to simultaneously reach a limit and the associated likely disturb affected memory blocks must all be checked at the same time. This gives rise to a variable and unpredictable degradation of the performance of SSD controllers in solid-state storage devices with a direct influence on the performance seen by a host device. Accordingly, there is a long felt need to avoid the aforementioned problems.